1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a high performance capacitor.
2. Description of the Related Art
In ICs (Integrated circuits) handling analog signals, passive devices such as capacitance elements, resistance elements, and inductance elements are important constituent elements for integrated circuits. Since it has been difficult to build in such passive devices in IC chips, the passive devices have been mounted as external parts on mounting boards. However, in view of requirement for increase in the operation speed and space saving of systems in recent years, attempts for incorporating such passive devices to the inside of IC chips have been made vigorously.
An MIM (Metal-Insulator-Metal) capacitor of sandwiching a dielectric film between metal electrodes has recently attracted attention as a method of forming a capacitor in the IC chip. This has a feature suitable for the use for high frequency operation due to less coupling resistance since the upper and lower electrodes can be formed with metal interconnects of low sheet resistance and low coupling resistance since it can be formed in a multilevel interconnect layer. However, since silicon oxide having a specific dielectric constant of 3.9 or silicon nitride having a specific dielectric constant of 7.0 has been mainly used so far as a capacitance dielectric film, a large area is necessary in a case of forming a capacitor of large capacitance to result in a problem of increasing the chip area and increasing the chip cost. As a method capable of overcoming the problem, MIM capacitors using a high-k film (dielectric film of high dielectric constant) have been noted in recent years.
The feature and the problem of the MIM capacitor using the high-k film are to be described with reference to an existent example described in JP-A-2004-214304 (Patent Document 1) shown in FIG. 2.
As shown in FIG. 2, after forming a first interlayer dielectric film 300 comprising silicon oxide from tetraethoxy silane as the starting material by using a plasma CVD method on a substrate in which a semiconductor device is formed, an opening is formed to the first interlayer dielectric film 300, and the opening was filled with a conductive plug 250 comprising tungsten. Then, after forming a second interlayer dielectric film 301 comprising silicon oxide of 1 μm thickness from tetraethoxy silane as a starting material by using a plasma CVD method, an opening was formed to a desired region to expose the conductive plug 250. Then, after forming titanium nitride of 50 nm film thickness, a lower electrode 200 comprising titanium nitride was left only in the region inside the opening formed in the second interlayer dielectric film 301 by using a lithographic method, and a dry etching method. Then, after forming a first capacitance film 400 comprising an HfAlO film (hafnium oxide film containing aluminum) of 20 nm thickness by using an ALD method (Atomic layer Deposition method), a titanium nitride film of 50 nm thickness was formed, and an upper electrode 201 was formed so as to cover the opening formed in the second interlayer dielectric film 301 by a lithographic method and a dry etching method. By the steps described above, an MIM capacitor comprising the lower electrode 200, the first capacitance film 400, and the upper electrode 201 can be formed. The MIM capacitor formed according to the steps described above is to be referred to as Existent Example 1 (refer to Patent Document 1).
In the MIM capacitor according to Conventional Example 1, since the HfAlO film having a specific dielectric constant of about 20 is used as a capacitance film, a capacitor of a large capacitance can be formed in a small area and the problem involved in the MIM capacitor using silicon oxide or silicon nitride as the capacitance film can be overcome.
However, the MIM capacitor constituted as described above has a drawback that a small capacitance cannot be formed easily at a high accuracy.
As a method of overcoming the problem, it has been proposed a method of using a capacitance film of low capacitance density for a capacitor requiring accuracy for the capacitance. Since the variation of the capacitance caused by the fabrication fluctuation can be restricted in a case where the capacitance density is low, even a capacitor of a small size can be formed at a high accuracy with less variation. An existent example of a step of forming such an MIM capacitor is to be described with reference to FIG. 3 (JP-A-2004-152796 (Patent Document 2)).
As shown in FIG. 3, after forming a first interlayer dielectric film 300 by using a plasma CVD method from tetraethoxy silane as a starting material on a substrate formed with a semiconductor device, and after forming titanium nitride of 50 nm film thickness and silicon nitride of 20 nm film thickness, a first fabricated capacitance film 401 comprising silicon nitride of 20 nm film thickness was formed only to a desired region by using a lithographic method and a dry etching method. Then, after forming HfAlO of 20 nm film thickness and titanium nitride of 50 nm film thickness successively, a first lower electrode 202 and a second lower electrode 203 comprising titanium nitride, a first fabricated capacitance film 401 comprising silicon nitride, a second fabricated capacitance film 402 and a third fabricated capacitance film 403 comprising HfAlO, and a first upper electrode 204 and a second upper electrode 205 comprising titanium nitride were formed by the combination of a lithographic method and a dry etching method. Then, after forming a second interlayer dielectric film 301 comprising silicon oxide of 1 μm thickness by using a plasma CVD method and after planarizing the same by a chemical-mechanical polishing method and after forming openings in the second interlayer electric film 301 so as to expose the first upper electrode 204 and the second upper electrode 205, a tungsten film was formed so as to fill the openings by using a sputtering method and a CVD method, and the tungsten film in the region other than the openings was removed by using chemical-mechanical polishing to form a first conductive plug 251 and a second conductor plug 252. Then, an aluminum film of 500 nm thickness was formed by a sputtering method and a metal interconnect 206 connected with the first conductive plug and a metal interconnect 207 connected with the second conductive plug were formed by using a lithographic method and a dry etching method. By the steps described above, a semiconductor device having an MIM capacitor comprising the first lower electrode 202, the first fabricated capacitance film 401, the fabricated third capacitance film 403, and the first upper electrode 204 (referred to as type A) and an MIM capacitor comprising the second lower electrode 203, the second fabricated capacitance film 402, and the second upper electrode 205 (referred to as type B) can be formed. The MIN capacitor formed in accordance with the steps described above is referred to as Conventional Example 2 (refer to Patent Document 2)
The MIM capacitor according to Conventional Example 2 is identical with Conventional Example 1 in that the fabrication fluctuation for the upper electrode or the lower electrode results in the variation of capacitance. However, according to Conventional Example 2, since capacitors of different capacitance densities can be formed simultaneously, high capacitance density and high capacitance accuracy can be satisfied together by using a capacitor of high capacitance density for the capacitor of large capacitance (type B capacitor) and using a capacitor of high capacitance accuracy (type A capacitor) in a case of intending to suppress the capacitance variation with a small area.